The disclosed embodiments of the present invention relate to an operating frequency adjusting scheme, and more particularly, to a method for adjusting operating frequency applied to a digitally-controlled oscillator (DCO) of an electronic device, such as an all-digital phase-locked loop (ADPLL).
The phase-locked loop (PLL) is widely used in wireless communications fields, and can dynamically reduce frequency offset between a received signal and a locally generated carrier. To a deep-submicron radio frequency (RF) process, such as the 28 nm process, a digital PLL is preferred rather than an analog PLL. This is because digital calibrations can relax analog requirements of the system and provide some potential benefits, such as higher performance, lower power and lower cost. Hence, the all-digital phase locked loop (ADPLL) implemented in purely digital circuitry is widely used in the deep-submicron RF process.
The transmitter to receiver (Tx-to-Rx) band noise specification of the ADPLL is crucial for ensuring quality of mobile communication systems. A stringent scenario may occur when the Tx power is at a maximum level while the sensitivity of the Rx signal power is insufficient. As shown by Table 1 below, some Tx bands may have relatively smaller band separation between the Tx band and the Rx band (hereinafter “Tx-to-Rx band separation”). For example, Band 2 has only 80 MHz band separation. Issues such as interference and crosstalk may occur in Band 2 due to the insufficient Tx-to-Rx band separation.
TABLE 1Tx-to-Rx band BandTx bandseparation (MHz)Rx band11920-19801902110-217021850-1910801930-1990
Hence, there is a need for an innovative ADPLL design which is capable of providing enough Tx-to-Rx band separation to achieve better transmission performance.